Power Simulation and Estimation in VLSI Circuits

In the past the major concerns of the VLSI designer were area speed and cost power consideration was typically of secondary importance In recent years how ever this has begun to change and increasingly power is being given comparable weight to other design considerations Several factors have contributed to this trend including the remarkable success and growth of the class of battery powered per sonal computing devices and wireless communications systems that demand high speed computation and complex functionality with low power consumption In these applications extending the battery service life is a critical design concern There also exists a signi cant pressure for producers of high end products to reduce their power consumption The main driving factors for lower power dissipation in these products are the cost associated with packaging and cooling as well as the circuit reliability System designers have started to respond to the requirement of power constrained system designs by a combination of architectural improvements and advanced design automation methodologies and technqiues for low power In parallel researchers and CAD tool developers have introduced a variety of models algorithms and techniques for estimating the power dissipation in VLSI circuits and systems in support of the low power optimization and synthesis techniques This article describes representative contributions to the power modeling and esti mation of VLSI circuits at various levels of design abstraction